Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Katsumata, et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. The structure described in Katsumata et al. includes a vertical NAND gate, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming a so-called gate all around cell at each layer, as illustrated by FIG. 1.
FIG. 1 is a horizontal cross-section of a column of a pipe-shaped BiCS flash cell, such as described in the Katsumata et al. publication, at the level of a word line. The structure includes a pillar 10 of semiconductor material which extends vertically through a stack of word line layers. The pillar 10 may have a seam 11 through the middle that arises from the deposition technique. A dielectric charge trapping structure comprising for example a first layer 12 of silicon oxide, a layer 13 of silicon nitride and a second layer 14 of silicon oxide (referred to as ONO), or another multilayer dielectric charge trapping structure surrounds the pillar 10. A gate all-around word line is intersected by the pillar. A frustum of the pillar at each layer combines with the gate all-around word line structure at that layer, to form a memory cell.
For the purposes of high density memory devices, it is desirable to have the channel diameter of the pillar 10 as small as possible. However, as the channel diameter shrinks, approaching for example 40 nm or less, the field enhancement factor by which the electric field between the word line 15 and the pillar 10 is intensified at the channel surface, can lead to problems with disturbance of charge trapped in the memory cells during read operations and program operations. As a result, the reliability of the structure degrades.
Katsumata et al. has suggested that the structure can be implemented using multiple-bit-per-cell programming technologies. These multiple-bit-per-cell programming technologies require fine control over threshold voltages, making read and program disturb characteristics even more critical. Therefore, even with high density three-dimensional flash technologies, the density of data storage can be limited.
Because of the relatively large cross-section of the column and dielectric charge trapping structure used to limit disturbance, the density of the three-dimensional memory structure is limited.
It is desirable to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, including reliable, very small memory elements, and high data densities.